Pixel clock frequency and optimum sampling phase adjustment is an important requirement in flat panel display monitors (FPDM) with an analog video interface. This invention proposes a new and more advanced method for frequency and optimum sampling phase determination. It is based on analyzing the content of the image to arrive at an optimum value of phase and frequency by directly optimizing image quality. The method differs from existing methods on two counts. First, no assumptions are needed about the precise value of expected frequency. Second, instead of following a two step approach of first determining frequency and then phase, this invention makes possible a single pass phase-frequency optimization.
Transfer of pixels, lines and frames from the PC to the monitor follows a predefined and synchronous timing format. Besides the active data transfer period, inactive regions are required on top, bottom, left and right of a frame. In CRT monitors this time is allocated for retrace of the electron beam from end of one line to the beginning of the next line, or from end of a frame to beginning of the next frame. In LCD monitors, various housekeeping functions are performed by the drive electronics during the inactive region. FIG. 1 shows the timing relationships between pixels, lines and frames. The Pixel Clock controls the basic pixel transmission rate. HSYNC is the horizontal synchronization frequency and marks the beginning of each line. Similarly VSYNC is used for vertical synchronization and marks the beginning of each frame. Data Enable (DE) is valid for the active period during which pixel data is transmitted.
Standard analog video interface between the PC and the monitor consists of the three RGB signals as well as horizontal and vertical synchronization signals. In Flat panel displays where the analog RGB video signals have to be converted into a digital format, it is important to sample the incoming signal at the pixel clock rate at an optimum sampling phase.
An example of vertical pin-stripe image highlights the importance of frequency and phase optimization. FIG. 2 shows the relationship between incoming video data and sampling clock phase and frequency. For a vertical pinstripe image, alternating dark and bright pixels constitute the data signals. Due to channel bandwidth limitations, the data signals have a finite risetime. If the frequency of sampling is different from the pixel clock, the sampled data points do not correspond to actual pixel data. Consequently, vertical bands appear on the screen due to aliasing in the frequency domain. In addition, the active width of the image is modified. If the frequency but sampling phase is not optimum, differences in values of two consecutive pixels becomes small leading to poor contrast in the image. Determining the correct pixel clock frequency and finding the optimum sampling phase are crucial to obtain high quality images.